//handle writes
module dflop(/*AUTOARG*/
   // Outputs
   read_data1, read_data2, read_data3, read_data4,
   // Inputs
   clk, reset, w_data1, w_data2, wen1, wen2, wr1, wr2, ren1, ren2,
   ren3, ren4
   );

input clk;
input reset;
input w_data1;
input w_data2;
input wen1;
input wen2;
input wr1;
input wr2;
input ren1;
input ren2;
input ren3;
input ren4;
output read_data1;
output read_data2;
output read_data3;
output read_data4;

reg q;
reg rd1,rd2,rd3,rd4;
wire enableflop;

assign enableflop1 = (wr1 & wen1);
assign enableflop2 = (wr2 & wen2);

always @ (negedge clk or negedge reset)
begin
	if (!reset) 
		q<= 1'b0;
	else
		if (enableflop1) 
			q<=w_data1;
		else
			if(enableflop2)
				q<=w_data2;	
end

always @ (ren1)
begin
	case(ren1)
		1 : rd1 <= q;
		0 : rd1 <= 1'b0;
	endcase
end

always @ (ren2)
begin
	case(ren2)
		1 : rd2 <= q;
		0 : rd2 <= 1'b0;
	endcase
end

always @ (ren3)
begin
	case(ren3)
		1 : rd3 <= q;
		0 : rd3 <= 1'b0;
	endcase
end

always @ (ren4)
begin
	case(ren4)
		1 : rd4 <= q;
		0 : rd4 <= 1'b0;
	endcase
end


/*
always @ (posedge clk or negedge reset)
begin
	if (!reset) 
		rd1<= 1'b0;
	else
		if (ren1) 
			rd1<=q;
		else 
			rd1<=1'b0;
end

always @ (posedge clk or negedge reset)
begin
	if (!reset)
		rd2<= 1'b0;
	else
		if (ren2) 
			rd2<=q;
		else 
			rd2<=1'b0;
end 

always @ (posedge clk or negedge reset)
begin
	if (!reset)
		rd3<= 1'b0;
	else
		if (ren3) 
			rd3<=q;
		else 
			rd3<=1'b0;
end 

always @ (posedge clk or negedge reset)
begin
	if (!reset)
		rd4<= 1'b0;
	else
		if (ren4) 
			rd4<=q;
		else 
			rd4<=1'b0;
end 
*/
assign read_data1 = rd1;
assign read_data2 = rd2;
assign read_data3 = rd3;
assign read_data4 = rd4;

endmodule
